Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
Conventional substrate fabrication utilizes a multi-step processing technique, which includes multiple etching steps performed in different process chambers. For example, multiple layers including a photoresist and one or more antireflective layers (e.g., a bottom antireflective coating, a tri-layer resist, or the like) may be formed atop one or more layers of the substrate and successively etched. Following the etch processes a post-etch stripping process is performed to remove the photoresist, antireflective materials and any residue thereof. However, conventional post etch stripping processes are time consuming and inefficient. For example, in some instances, where no or low bias power is provided, the removal rate may undesirably lessen, and the process may fail to completely remove the residual materials. Alternatively, in some instances where high bias power is provided, undesirable etching of underlying layers (e.g., metal layers) may occur. As such, the inventors have provided a new process that provides excellent photoresist to metal layer selectivity, allowing for rapid processing without undesired etching of the metal material.